آی پی کور 16بیتی 80186 با نام s80186 قابل یکپارچه سازی در طراحی های FPGA و ASIC :
S80186: 16-bit 80186 compatible IP core
The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The core executes most instructions in far fewer cycles than the original Intel 8086, and in many cases, fewer cycles than the 80286. The core is supplied as synthesizable SystemVerilog, along with a C++ reference model, extensive tests, a reference BIOS implementation and reference FPGA designs.
https://www.jamieiles.com/80186/
https://github.com/jamieiles/80x86
@Taksuntec
S80186: 16-bit 80186 compatible IP core
The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The core executes most instructions in far fewer cycles than the original Intel 8086, and in many cases, fewer cycles than the 80286. The core is supplied as synthesizable SystemVerilog, along with a C++ reference model, extensive tests, a reference BIOS implementation and reference FPGA designs.
https://www.jamieiles.com/80186/
https://github.com/jamieiles/80x86
@Taksuntec
Jamieiles
Jamie Iles - Computer Systems Engineer | 80186 CPU
Jamie Iles: Software craftsman skilled in C, C++, Python, Linux, security, hardware and technical leadership.
زایلینکس چیپ اولترا اسکیل پلاس VU23P را با بهینه سازی مختص شبکه ای و شتابدهی حافظه معرفی کرد :
Introducing the Virtex UltraScale+ VU23P #FPGA: Optimized for Adaptable Networking and Storage Acceleration
- Highest ratio of LUTs and block RAM to DSP slices in the Virtex UltraScale+ portfolio
لبنک معرفی :
https://forums.xilinx.com/t5/Xilinx-Xclusive-Blog/Born-to-Run-New-Virtex-UltraScale-FPGA-optimized-for-networking/ba-p/1108726
جرییات :
https://www.xilinx.com/publications/product-briefs/xilinx-virtex-ultrascale-vu23p-fpga-product-brief.pdf
@Taksuntec
Introducing the Virtex UltraScale+ VU23P #FPGA: Optimized for Adaptable Networking and Storage Acceleration
- Highest ratio of LUTs and block RAM to DSP slices in the Virtex UltraScale+ portfolio
لبنک معرفی :
https://forums.xilinx.com/t5/Xilinx-Xclusive-Blog/Born-to-Run-New-Virtex-UltraScale-FPGA-optimized-for-networking/ba-p/1108726
جرییات :
https://www.xilinx.com/publications/product-briefs/xilinx-virtex-ultrascale-vu23p-fpga-product-brief.pdf
@Taksuntec
Xilinx
Born to Run: New Virtex UltraScale+ FPGA optimized for networking and storage acceleration
The exponential growth of data demands smart and adaptable network and data center solutions that deliver maximum throughput, high data-processing capability and the flexibility to adapt to evolving connectivity standards. To meet all of these requirements…
اغلب مهندسان برق با قانون مور آشنا هستند. این قانون روند دو برابر شدن تعداد ترانزیستورها را در یک دوره زمانی ثابت پیش بینی کرده است که تاکنون پایدار مانده است. این قانون تنها اعجاز آن مقاله نبوده است. در مقاله مور باعنوان جا دادن اجزای بیشتر در آی سی ها تصویری وجود دارد که شخصی کامپیوترهای بسیار کوچک به صورت امبدد را میفروشد و بیشتر انسان ها در کنار سایر مغازه ها مانند فروشگاه وسایل آرایشی تنها به آن توجه دارند.
این مقاله در سال 1965 ارائه شده است
لینک مقاله :
https://hasler.ece.gatech.edu/Published_papers/Technology_overview/gordon_moore_1965_article.pdf
@Taksuntec
این مقاله در سال 1965 ارائه شده است
لینک مقاله :
https://hasler.ece.gatech.edu/Published_papers/Technology_overview/gordon_moore_1965_article.pdf
@Taksuntec
ثبت نام رایگان کورس های مدرسه تابستانی ACACES 2020:
16th International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems
نمونه ای از ارائه ها :
- Exploiting the Benefits of Graphics Processing Units: Programming, Architectures and Simulation
-Working with RISC-V: from open ISA to open Architecture to open Hardware
- Machine Learning Accelerators
-Intellectual Property Rights as a Business Tool
https://www.hipeac.net/acaces/2020/#/
@Taksuntec
16th International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems
نمونه ای از ارائه ها :
- Exploiting the Benefits of Graphics Processing Units: Programming, Architectures and Simulation
-Working with RISC-V: from open ISA to open Architecture to open Hardware
- Machine Learning Accelerators
-Intellectual Property Rights as a Business Tool
https://www.hipeac.net/acaces/2020/#/
@Taksuntec
Forwarded from Sam Ghanizadeh
#پروژه کسری خدمت و نخبگان | امریه | فرصت شغلی
عنوان:استخدام/کسر خدمت FPGA
رشته تحصیلی مورد نیاز:
#مهندسی برق - الکترونیک | مهندسی برق - مخابرات
مقطع تحصیلی:
#کارشناسی ارشد
زمینه های مورد نیاز:
2- مهندس الکترونیک / مخابرات سیستم مسلط به FPGA و ترجیحا آشنا به سیستم های مخابراتی
🏢 موقعیت مکانی:
پارک فناوری دانشگاه تهران
ارسال رزومه :
تلگرام : @reyhanezmn
عنوان:استخدام/کسر خدمت FPGA
رشته تحصیلی مورد نیاز:
#مهندسی برق - الکترونیک | مهندسی برق - مخابرات
مقطع تحصیلی:
#کارشناسی ارشد
زمینه های مورد نیاز:
2- مهندس الکترونیک / مخابرات سیستم مسلط به FPGA و ترجیحا آشنا به سیستم های مخابراتی
🏢 موقعیت مکانی:
پارک فناوری دانشگاه تهران
ارسال رزومه :
تلگرام : @reyhanezmn
آموزش چگونگی ارائه یک اپلیکیشن FPGA به صورت Container:
HOW TO CONTAINERIZE AN FPGA APPLICATION?
After months of development & testing, your FPGA application is finally ready to be delivered to your customers.
You will now encounter the usual deployment conundrum: user environment fragmentation.
Every user will have its own, customized, execution environment with the different kernel, OS, libs…and your FPGA application needs to be compatible with all of them.
To tackle this unsolvable equation, there is one straightforward solution: Containers!
https://www.accelize.com/blog/how-containerize-fpga-application
@Taksuntec
HOW TO CONTAINERIZE AN FPGA APPLICATION?
After months of development & testing, your FPGA application is finally ready to be delivered to your customers.
You will now encounter the usual deployment conundrum: user environment fragmentation.
Every user will have its own, customized, execution environment with the different kernel, OS, libs…and your FPGA application needs to be compatible with all of them.
To tackle this unsolvable equation, there is one straightforward solution: Containers!
https://www.accelize.com/blog/how-containerize-fpga-application
@Taksuntec
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ویدوای جالب از برنامه نویسی وکتور و SIMD روی پردازنده X86 با ویژوال استودیو
@Taksuntec
@Taksuntec
شرکت تولید کننده نیمه های لتیس آخرین بسته نرم افزاری SDK خود را منتشر کرد، در این بسته قابلیت مهندسی معکوس بیت استریم ها مورد هدف بوده است :
https://hackaday.com/2020/06/05/lattice-semiconductor-targets-bitstream-reverse-engineering-in-latest-propel-sdk-license/
https://www.latticesemi.com/propel
@Taksuntec
https://hackaday.com/2020/06/05/lattice-semiconductor-targets-bitstream-reverse-engineering-in-latest-propel-sdk-license/
https://www.latticesemi.com/propel
@Taksuntec
Hackaday
Lattice Semiconductor Targets Bitstream Reverse Engineering In Latest Propel SDK License
The topic of reverse engineering is highly contentious at best when it comes to software and hardware development. Ever since the configuration protocol (bitstream) for Lattice Semiconductor’…
زایلینکس نسخه جدید نرم افزارهای خود یعنی 2020.1 را اعم از VITIS و HLx را منتشر کرد:
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html
@Taksuntec
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html
@Taksuntec
AMD
Downloads
Vivado, Vitis, Vitis Embedded Platform, PetaLinux, Device models
ثبت نام وبینارهای مرتبط با پیاده سازی مدل های یادگیری ماشین و یادگیری عمیق بر روی میکروکنترلرهای آرم :
June 16, 2020
- Machine learning for embedded systems at the edge
June 30, 2020
- tinyML development with Tensorflow Lite for Microcontrollers and CMSIS-NN
July 14, 2020
- Demystify artificial intelligence on Arm MCUs
July 28, 2020
- Speech recognition on Arm Cortex-M
August 11, 2020
- Getting started with Arm Cortex-M software development and Arm Development Studio
August 25, 2020
- Efficient ML across Arm from Cortex-M to Web Assembly
https://developer.arm.com/solutions/machine-learning-on-arm/ai-virtual-tech-talks?_ga=2.56839983.408560827.1591724732-278917169.1591724732
@Taksuntec
June 16, 2020
- Machine learning for embedded systems at the edge
June 30, 2020
- tinyML development with Tensorflow Lite for Microcontrollers and CMSIS-NN
July 14, 2020
- Demystify artificial intelligence on Arm MCUs
July 28, 2020
- Speech recognition on Arm Cortex-M
August 11, 2020
- Getting started with Arm Cortex-M software development and Arm Development Studio
August 25, 2020
- Efficient ML across Arm from Cortex-M to Web Assembly
https://developer.arm.com/solutions/machine-learning-on-arm/ai-virtual-tech-talks?_ga=2.56839983.408560827.1591724732-278917169.1591724732
@Taksuntec
Arm Developer
AI and Machine Learning | AI Virtual Tech Talks series – Arm Developer
Tech Talks showcase Arm Engineers and Partners through live and recorded broadcasts
شرکت XILINX آیپی کور های MIPI یعنی رابط های صنعتی مانیتور و دوربین سریال DSI و CSI را رایگان میکند.
@Taksuntec
Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado | Hackaday
https://hackaday.com/2020/06/09/xilinx-makes-mipi-csi-and-dsi-controller-ip-blocks-free-to-use-with-vivado/
@Taksuntec
Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado | Hackaday
https://hackaday.com/2020/06/09/xilinx-makes-mipi-csi-and-dsi-controller-ip-blocks-free-to-use-with-vivado/
Hackaday
Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado
If you want to use a display or camera with an FPGA, you will often end up with a MIPI-based solution. As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camer…
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ساخت یک اینترفیس AXI master ساده برای تست در HLS با استفاده از ZYBO
لینک اصلی :
Creating a simple AXI master interface for testing with Vivado HLS
@Taksuntec
لینک اصلی :
Creating a simple AXI master interface for testing with Vivado HLS
@Taksuntec
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تغییرات نسخه 2020.01 ابزار زایلینکس :
What's New in Embedded Software and Tools 2020.1
سایز دانلود پتالینوکس از 8 گیگ به 1.5 گیگ کاهش پیدا کرده است!
@Taksuntec
What's New in Embedded Software and Tools 2020.1
سایز دانلود پتالینوکس از 8 گیگ به 1.5 گیگ کاهش پیدا کرده است!
@Taksuntec
مقاله ای جالب در مورد دلایل کم بودن درایورها برای FPGA :
FPGA: Why So Few Open Source Drivers for Open Hardware?
https://mupuf.org/blog/2020/06/09/FPGA-why-so-few-drivers/
@Taksuntec
FPGA: Why So Few Open Source Drivers for Open Hardware?
https://mupuf.org/blog/2020/06/09/FPGA-why-so-few-drivers/
@Taksuntec
www.mupuf.org
FPGA: Why so few open source drivers for open hardware? - mupuf.org
Field-Programmable Gate Arrays (FPGA) have been an interest of mine for well over a decade now. Being able to generate
complex signals in the tens of …
complex signals in the tens of …
ODROID-H2+ An x86 Board to Challenge Raspberry Pi?
https://www.tomshardware.com/uk/news/odroid-h2-an-x86-board-to-challenge-raspberry-pi
https://www.tomshardware.com/uk/news/odroid-h2-an-x86-board-to-challenge-raspberry-pi
Tom's Hardware
ODROID-H2+ An x86 Board to Challenge Raspberry Pi?
More power is better?
هسته تبدیل USB3.0 به AXI4 با استفاده از FTDI FT601 به زبان وریلاگ:
FTDI FT601 SuperSpeed USB3.0 to AXI bus master
https://github.com/ultraembedded/core_ft60x_axi
@Taksuntec
FTDI FT601 SuperSpeed USB3.0 to AXI bus master
https://github.com/ultraembedded/core_ft60x_axi
@Taksuntec
GitHub
GitHub - ultraembedded/core_ft60x_axi: FTDI FT600 SuperSpeed USB3.0 to AXI bus master
FTDI FT600 SuperSpeed USB3.0 to AXI bus master. Contribute to ultraembedded/core_ft60x_axi development by creating an account on GitHub.
مسابقه پیاده سازی الگوریتم طبقه بندی دیتاست ایمجنت بر رویV2 ultra96 :
جایزه بیست تیمی که زودتر سابمیت کنند ۲۷۰$
جایزه تیم اول ۱۵۰۰ دوم ۱۰۰۰ و سوم ۵۰۰ $
https://lpcv.ai/2020CVPR/image-track
@Taksuntec
جایزه بیست تیمی که زودتر سابمیت کنند ۲۷۰$
جایزه تیم اول ۱۵۰۰ دوم ۱۰۰۰ و سوم ۵۰۰ $
https://lpcv.ai/2020CVPR/image-track
@Taksuntec
lpcv.ai
LPCV - Low Power Computer Vision
The Low Power Computer Vision workshop will discuss the state of the art of low-power computer vision, challenges in creating efficient vision solutions, promising technologies that can achieve the goals, methods to acquire and label data, benchmarks and…